Semiconductor device comprising work function metal pattern in boundry region and method for fabricating the same

ABSTRACT

A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

This application is a continuation of U.S. application Ser. No. 16/890,456, filed on Jun. 2, 2020, which is a continuation of U.S. application Ser. No. 16/391,888 filed on Apr. 23, 2019, now granted as U.S. Pat. No. 10,679,997 on Jun. 9, 2020, which is a continuation of U.S. application Ser. No. 15/828,934 filed on Dec. 1, 2017, now granted as U.S. Pat. No. 10,332,894 on Jun. 25, 2019, which claims priority from Korean Patent Application No. 10-2017-0017632 filed on Feb. 8, 2017 in the Korean Intellectual Property Office, the disclosure of each of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present inventive concepts relate to a semiconductor device and/or a method of fabricating the same.

2. Description of the Related Art

A semiconductor memory element such as DRAM has a cell region and a core region. In particular, the core region includes a region in which a PMOS transistor is formed, and a region in which an NMOS transistor is formed. Recently, a structure is used in which a p-type gate is disposed in a region in which the PMOS transistor is formed and an n-type gate is disposed in a region in which the NMOS transistor is formed.

Further, as the degree of integration of the semiconductor memory element increases, a leakage current through the gate dielectric layer of the transistor increases. As a result, a gate dielectric layer is formed, using a high dielectric material (high-k dielectric material).

SUMMARY OF THE INVENTION

An aspect of the present inventive concepts provides a semiconductor device with improved degree of integration and reliability.

Another aspect provides a method for fabricating a semiconductor device with improved degree of integration and reliability.

The technical problem of the present inventive concepts is not limited to the technical problem mentioned above, and another technical problem which is not mentioned will be clearly understood by those skilled in the art from the following description.

According to some example embodiments of the present inventive concepts, there is provided a semiconductor device including, a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the substrate of the boundary region to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the substrate of the core region, a first work function metal pattern which includes a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern which includes a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension extending in a direction from the core region toward the cell region is different from a second length of the second extension extending in a direction from the core region toward the cell region.

According to some example embodiments of the present inventive concepts, there is provided a semiconductor device including, a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern including a first extension overlapping the boundary element isolation layer on the substrate, and a second work function metal pattern including a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein the boundary element isolation layer includes a recess, which does not overlap the first and second extensions, and is adjacent to at least one of the first and second extensions.

According to some example embodiments of the present inventive concepts, there is provided a semiconductor device including a cell region in a substrate, an element isolation layer around the cell region, a high-k dielectric layer extending onto a portion of the element isolation layer from a direction opposite from a direction of the cell region, a first work function metal pattern extending a first length onto the element isolation layer from the direction opposite from the direction of the cell region, and a second work function metal pattern extending a second length onto the element isolation layer from the direction opposite from the direction of the cell region. At least a portion of the second work function metal pattern is on the first work function metal pattern. The first work function metal pattern is on the high-k dielectric layer. The second length is different from the first length.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects and features of the present inventive concepts will become more apparent by describing in detail some example embodiments thereof with reference to the attached drawings, in which:

FIG. 1 is a layout diagram for illustrating a semiconductor device according to some example embodiments of the present inventive concepts.

FIG. 2 is an enlarged view of a region R of FIG. 1.

FIG. 3 is a cross-sectional view taken along lines A-A′, B-B′, and C-C′ of FIG. 1.

FIG. 4a is an enlarged view of a region D of FIG. 3.

FIG. 4b is a diagram for illustrating a boundary region of a semiconductor device according to some example embodiments of the present inventive concepts.

FIG. 4c is a diagram for illustrating a boundary region of a semiconductor device according to some example embodiments of the present inventive concepts.

FIGS. 5 to 16 are intermediate step diagrams for explaining a method for fabricating a semiconductor device according to some example embodiments of the present inventive concepts.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, a semiconductor device according to some example embodiments of the present inventive concepts will be described with reference to FIGS. 1 to 4 a.

FIG. 1 is a layout diagram for illustrating a semiconductor device according to some example embodiments of the present inventive concepts. FIG. 2 is an enlarged view of a region R of FIG. 1. FIG. 3 is a cross-sectional view taken along lines A-A′, B-B′, and C-C′ of FIG. 1. FIG. 4a is an enlarged view of a region D of FIG. 3.

Referring to FIG. 1, a semiconductor device according to some example embodiments of the present inventive concepts includes a cell region (CELL), a core region (CORE), and a boundary region (INTERFACE).

In the cell region (CELL), semiconductor cells may be disposed to form an array. For example, when the semiconductor device to be formed is a semiconductor memory device, semiconductor memory cells may be disposed in the cell region (CELL) to form an array.

The core region (CORE) may be disposed around the cell region (CELL) or may be disposed in another region different from the cell region (CELL). Some control elements and dummy elements may be formed in the core region (CORE). As a result, a circuit necessary for controlling the semiconductor cells formed in the cell region (CELL) may be disposed in the core region (CORE).

The boundary region (INTERFACE) may be disposed between the cell region (CELL) and the core region (CORE). Specifically, the boundary region (INTERFACE) may be disposed to be adjacent to the cell region (CELL) and the core region (CORE) between the cell region (CELL) and the core region (CORE). For example, as illustrated in FIG. 1, the boundary region (INTERFACE) may be disposed between the cell region (CELL) and the core region (CORE) disposed around the cell region (CELL). As a result, the boundary region (INTERFACE) may wrap around the cell region (CELL).

A boundary element isolation layer (110 a of FIG. 3) may be disposed in the boundary region (INTERFACE). As a result, the boundary region (INTERFACE) may separate the cell region (CELL) from the core region (CORE).

Referring to FIG. 2, an active region AR, a word line WL, a bit line BL and a direct contact DC may be disposed in the cell region (CELL).

The active region AR may be defined by the element isolation layer (110 of FIG. 3).

As the design rule of the semiconductor device decreases, the active region AR may be disposed in the form of a diagonal bar. Specifically, the active region AR may be disposed in the form of bar extending in an arbitrary direction other than the first direction X and the second direction Y, on the plane in which the first direction X and the second direction Y extend.

Also, the active region AR may be in the form of a plurality of bars extending in the directions parallel to each other. At this time, the center of one active region AR of the plurality of active regions AR may be disposed to be adjacent to the distal end of the other active region AR.

Impurities may be implanted into the active region AR to form source and drain regions. Implantation of the impurities into the active region AR may be performed in an ion implantation process, but the example embodiments of the present disclosure are not limited thereto.

The word line WL may extend along the first direction X across the active region AR. A plurality of word lines WL may extend in parallel to each other and may be spaced apart from each other at equal intervals. For example, the plurality of word lines WL may be buried in the substrate (100 of FIG. 3) to extend parallel to each other and may be spaced apart from each other at equal intervals.

The bit line BL may extend along the second direction Y different from the first direction X across the active region AR and the word line WL. For example, the second direction Y may be a direction orthogonal to the first direction X. Therefore, the bit line BL may diagonally across the active region AR and may vertically across the word line WL.

A plurality of bit lines BL may extend parallel to each other and may be spaced apart from each other at equal intervals. For example, the plurality of bit lines BL may extend parallel to each other on the substrate (100 of FIG. 3) and may be spaced apart from each other at equal intervals.

The direct contact DC may be disposed at the center of the active region AR. Further, the direct contact DC may be electrically connected to the bit line BL. As a result, the center of the active region AR may be electrically connected to the bit line BL.

Referring to FIG. 3, the semiconductor device according to some example embodiments of the present inventive concepts includes a substrate 100, an element isolation layer 110, a word line pattern 120, first and second insulating layers 202 and 204, a bit line pattern 220, a direct contact pattern 210, a capping layer 230, a gate insulating layer 130, a high-k dielectric layer 140, first and second work function metal patterns 150′ and 160′ and a gate spacer 240.

The substrate 100 may have a structure in which a base substrate and an epitaxial layer are laminated, but the present disclosure is not limited thereto. The substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, a display glass substrate or the like, and may be an SOI (semiconductor on insulator) substrate. As an example, the substrate 100 may be a silicon substrate.

The substrate 100 includes a cell region (CELL), a core region (CORE), and a boundary region (INTERFACE). At this time, the core region (CORE) may include first and second regions I and II. As illustrated, the first and second regions I and II may be disposed to be spaced apart from each other, but the example embodiments of the present disclosure are not limited thereto, and the first and second regions I and II may be disposed to be adjacent to each other.

In some example embodiments, conductive transistors different from each other may be formed in the first and second regions I and II. For example, a PMOS transistor may be formed in the first region I, and an NMOS transistor may be formed in the second region II. In this case, the substrate 100 of the first region I may be doped with an n-type impurity, and the substrate 100 of the second region II may be doped with a p-type impurity.

The element isolation layer 110 may define an active region (AR of FIG. 2) disposed on the top of the substrate 100. The element isolation layer 110 may include silicon oxide, silicon nitride or a combination thereof, but the example embodiments of the present disclosure are not limited thereto. The element isolation layer 110 may be a single layer made of one kind of insulating material or may be multi-layers made up of combinations of several kinds of insulating materials.

The element isolation layer 110 may include a boundary element isolation layer 110 a disposed in the boundary region (INTERFACE). That is, the boundary element isolation layer 110 a may be disposed in the substrate 100 of the boundary region (INTERFACE). Therefore, the boundary element isolation layer 110 a may separate the cell region (CELL) from the core region (CORE). That is, the boundary region (INTERFACE) may be defined by the boundary element isolation layer 110 a.

The boundary element isolation layer 110 a may include a recess 110 r on its upper surface. This will be specifically described later in the description of FIG. 4 a.

The word line pattern 120 may be disposed on the substrate 100 of the cell region (CELL). The word line pattern 120 may include a buried dielectric layer 126, a buried conductive layer 124, and a buried insulating layer 122. The word line pattern 120 may correspond to the word line WL of FIG. 2. That is, the word line pattern 120 may extend in the first direction X. For example, as illustrated in FIG. 3, the word line pattern 120 may be buried in the substrate 100 of the cell region (CELL) to extend in the first direction X.

Specifically, a word line trench extending in the first direction X may be formed on the substrate 100. At this time, the lower surface of the word line trench may be higher than the lower surface of the element isolation layer 110. The buried dielectric layer 126 may be disposed along the word line trench. Further, the buried conductive layer 124 and the buried insulating layer 122 may be sequentially laminated on the buried dielectric layer 126. As a result, the buried dielectric layer 126, the buried conductive layer 124, and the buried insulating layer 122 may fill the word line trench to form the word line pattern 120. At this time, the buried conductive layer 124 may be electrically insulated from the substrate 100 by the buried dielectric layer 126.

As illustrated, the word line pattern 120 may be disposed on the element isolation layer 110. However, the present disclosure is not limited thereto, and the word line pattern 120 may not be disposed on the element isolation layer 110.

The first and second insulating layers 202 and 204 may be disposed on the substrate 100 and the element isolation layer 110. Specifically, the first and second insulating layers 202 and 204 may be disposed on the substrate 100, the element isolation layer 110, and the word line pattern 120 of the cell region (CELL).

The first and second insulating layers 202 and 204 may include materials different from each other. For example, the first insulating layer 202 may contain silicon oxide, and the second insulating layer 204 may contain silicon nitride. However, the example embodiments of the present disclosure are not limited thereto, and the first and second insulating layers 202 and 204 may be formed of a single layer containing the same material. Further, each of the first and second insulating layers 202 and 204 may be formed of multi-layers, respectively.

The bit line pattern 220 may be disposed on the substrate 100. The bit line pattern 220 may correspond to the bit line BL of FIG. 2. That is, the bit line pattern 220 may extend in the second direction Y on the substrate 100 of the cell region (CELL). Specifically, the bit line pattern 220 may be disposed on the first and second insulating layers 202 and 204.

The bit line pattern 220 may be a single layer, but may be multi-layers including the first to third conductive layers 222, 224 and 226 as illustrated. That is, the bit line pattern 220 may be formed by sequentially disposing the first to third conductive layers 222, 224 and 226 on the first and second insulating layers 202 and 204.

Each of the first to third conductive layers 222, 224, and 226 may include polysilicon, TiN, TiSiN, tungsten, tungsten silicide or a combination thereof. For example, the first conductive layer 222 may contain polysilicon, the second conductive layer 224 may contain TiSiN, and the third conductive layer 226 may contain tungsten. However, the example embodiments of the present disclosure are not limited thereto.

The direct contact pattern 210 may be disposed on the substrate 100 of the cell region (CELL) through the first and second insulating layers 202 and 204. The direct contact pattern 210 may correspond to the direct contact DC of FIG. 2. That is, the direct contact pattern 210 is disposed on the substrate 100 and may be electrically connected to the bit line pattern 220. As a result, the substrate 100 disposed below the direct contact pattern 210 may be electrically connected to the bit line pattern 220.

The capping layer 230 may be disposed on the bit line pattern 220. That is, the capping layer 230 may extend in the second direction Y on the bit line pattern 220 of the cell region (CELL).

The capping layer 230 may contain silicon nitride, but the example embodiments of the present disclosure are not limited thereto.

The gate insulating layer 130 may be disposed on the substrate 100 of the core region (CORE). Specifically, the gate insulating layer 130 may be disposed on the substrate 100 of the core region (CORE) adjacent to the boundary region (INTERFACE). Further, the gate insulating layer 130 may be disposed in a part on the substrate 100 of the first region I, and may be disposed in a part on the substrate of the second region II. However, the example embodiments of the present disclosure are not limited thereto, and the gate insulating layer 130 may be disposed on the element isolation layer 110 of the core region (CORE). Further, the gate insulating layer 130 disposed on the substrate 100 of the core region (CORE) adjacent to the boundary region (INTERFACE) may further extend in the second direction Y, and may be disposed on the boundary element isolation layer 110 a.

The gate insulating layer 130 disposed on the substrate 100 of the first and second regions I and II may extend in the first direction X. However, the example embodiments of the present disclosure are not limited thereto, and the gate insulating layer 130 may extend in various directions. For example, the gate insulating layer 130 may also extend in the second direction Y.

Further, the gate insulating layer 130 may extend in the directions different from each other in the first and second regions I and II. For example, the gate insulating layer 130 disposed on the substrate 100 of the first region I may extend in the first direction X, and the gate insulating layer 130 disposed on the substrate 100 of the second region II may extend in the second direction Y.

The gate insulating layer 130 may contain silicon oxide, but the example embodiments of the present disclosure are not limited thereto.

The high-k dielectric layer 140 may be disposed on the substrate 100 of the boundary region (INTERFACE) and the core region (CORE). Specifically, the high-k dielectric layer 140 may be disposed on at least a part of the boundary element isolation layer 110 a in the boundary region (INTERFACE). Further, the high-k dielectric layer 140 may be disposed on the gate insulating layer 130 in the core region (CORE).

The high-k dielectric layer 140 may contain silicon oxide, silicon nitride, silicon oxynitride ONO (oxide/nitride/oxide) or a high-k dielectric material having a dielectric constant than higher silicon oxide.

For example, the high-k dielectric layer 140 may contain hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminium oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), lead scandium tantalum oxide (PbScTaO) or a combination thereof. However, the example embodiments of the present disclosure are not limited thereto.

Although not illustrated, an interface layer may be further interposed between the gate insulating layer 130 and the high-k dielectric layer 140. The interface layer may prevent a defective interface between the gate insulating layer 130 and the high-k dielectric layer 140.

The first work function metal pattern 150′ may be disposed on the substrate 100 of the boundary region (INTERFACE) and the core region (CORE). Specifically, the first work function metal pattern 150′ may be disposed on the boundary element isolation layer 110 a or the high-k dielectric layer 140 in the boundary region (INTERFACE). Further, the first work function metal pattern 150′ may be disposed on the high-k dielectric layer 140 in the first region I.

However, the first work function metal pattern 150′ may not be disposed in the second region II. That is, the first work function metal pattern 150′ may be disposed on the high-k dielectric layer 140 of the first region I, and may not be disposed on the substrate 100 of the second region II.

In some example embodiments, the first region I may be a region in which the PMOS transistor is formed. That is, the substrate 100 of the first region I may be doped with an n-type impurity. That is, the first work function metal pattern 150′ disposed on the high-k dielectric layer 140 of the first region I may be a metal layer which adjusts the threshold voltage of the PMOS transistor.

For example, the first work function metal pattern 150′ may be formed of tungsten (W), tantalum (Ta), aluminum (Al), ruthenium (Ru), platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), or a combination thereof, but the example embodiments of the present disclosure are not limited thereto.

Further, the first work function metal pattern 150′ may be formed of a multi-layer structure in which a plurality of thin metal layers is laminated. For example, the first work function metal pattern 150′ may be formed of Al₂O₃/TiN, Al₂O₃/TaN, Al/TiN, Al/TaN, TiN/Al/TiN, TaN/Al/TaN, TiN/TiON, TaN/TiON, Ta/TiN, TaN/TiN, or combinations thereof.

The second work function metal pattern 160′ may be disposed on the substrate 100 of the boundary region (INTERFACE) and the core region (CORE). Specifically, the second work function metal pattern 160′ may be disposed on the boundary element isolation layer 110 a, the first work function metal pattern 150′ or the high-k dielectric layer 140 in the boundary region (INTERFACE). Further, the second work function metal pattern 160′ may be disposed on the high-k dielectric layer 140 in the core region (CORE).

More specifically, the second work function metal pattern 160′ may be disposed on the first work function metal pattern 150′ in the first region I. Further, the second work function metal pattern 160′ may be disposed on the high-k dielectric layer 140 in the second region II. That is, the second work function metal pattern 160′ may be disposed on the first work function metal pattern 150′ of the first region I, and may be disposed on the high-k dielectric layer 140 of the second region II.

In some example embodiments, the second region II may be a region in which the NMOS transistor is formed. That is, the substrate 100 of the second region II may be doped with a p-type impurity. That is, the second work function metal pattern 160′ disposed on the high-k dielectric layer 140 of the second region II may be a metal layer which adjusts the threshold voltage of the NMOS transistor.

For example, the second work function metal pattern 160′ may contain lanthanum (La), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), titanium nitride (TiN), or a combination thereof. However, the example embodiments of the present disclosure are not limited thereto.

Further, the second work function metal pattern 160′ may also be formed of a multi-layer structure in which a plurality of thin metal layers is laminated. For example, the second work function metal pattern 160′ may be selected from TiN/TiON, Mg/TiN, TiN/Mg/TiN, La/TiN, TiN/La/TiN, Sr/TiN, TiN/Sr/TiN, or combinations thereof.

The first to third conductive layers 222, 224 and 226 may be disposed on the second work function metal pattern 160′. That is, the first to third conductive layers 222, 224 and 226 forming the bit line pattern 220 in the cell region (CELL) may also be disposed in the core region (CORE).

Specifically, the first to third conductive layers 222, 224 and 226 are sequentially laminated on the second work function metal pattern 160′ in the first and second regions I and II. Further, the first to third conductive layers 222, 224 and 226 may be laminated on the second work function metal pattern 160′ in the boundary region (INTERFACE). In some example embodiments, the first to third conductive layers 222, 224 and 226 may completely cover the second work function metal pattern 160′.

The capping layer 230 may be disposed on the first to third conductive layers 222, 224 and 226. That is, the capping layer 230 disposed on the bit line pattern 220 in the cell region (CELL) may also be disposed in the core region (CORE).

The gate spacer 240 may be disposed on side walls of the gate insulating layer 130, the high-k dielectric layer 140, and the first and second work function metal patterns 150′ and 160′.

Specifically, the gate spacer 240 may be disposed on the side walls of the gate insulating layer 130, the high-k dielectric layer 140, the first and second work function metal patterns 150′ and 160′, the first to third conductive layers 222, 224 and 226, and the capping layer 230 in the first region I.

Further, the gate spacer 240 may be disposed on the side walls of the gate insulating layer 130, the high-k dielectric layer 140, the second work function metal pattern 160′, the first to third conductive layers 222, 224 and 226, and the capping layer 230 in the second region II.

Hereinafter, the boundary region of the semiconductor device according to some example embodiments of the present inventive concepts will be specifically described with reference to FIGS. 3 and 4 a.

As described above, the high-k dielectric layer 140, the first work function metal pattern 150′, and the second work function metal pattern 160′ may be disposed on the substrate 100 of the boundary region (INTERFACE) and the core region (CORE).

Specifically, the high-k dielectric layer 140, the first work function metal pattern 150′ and the second work function metal pattern 160′ disposed on the substrate 100 of the core region (CORE) may extend in the direction toward the cell region (CELL) and may be disposed on the boundary region (INTERFACE). That is, a part of the high-k dielectric layer 140, a part of the first work function metal pattern 150′, and a part of the second work function metal pattern 160′ may be disposed on the boundary element isolation layer 110 a.

At this time, the portion of the first work function metal pattern 150′ overlapping the boundary element isolation layer 110 a may be defined as a first extension 150 a. Here, the expression “the first work function metal pattern 150′ overlaps the boundary element isolation layer 110 a” means that the first work function metal pattern 150′ includes a portion which overlaps the boundary element isolation layer 110 a in a third direction intersecting with the first and second directions X and Y.

Similarly, a portion of the second work function metal pattern 160′ overlapping the boundary element isolation layer 110 a may be defined as the second extension 160 a, and a portion of the high-k dielectric layer 140 overlapping the boundary element isolation layer 110 a may be defined as the third extension 140 a. That is, the first to third extensions 150 a, 160 a and 140 a overlap the first work function metal pattern 150′, the second work function metal pattern 160′ and the high-k dielectric layer 140 in the third direction Z, respectively.

Further, the first to third extensions 150 a, 160 a and 140 a may extend in the direction from the core region (CORE) toward the cell region (CELL), respectively. For example, the first to third extensions 150 a, 160 a and 140 a may extend in the second direction Y.

In some example embodiments, a first length L1 a in which the first extension 150 a extends in the second direction Y may be shorter than a second length L2 a in which the second extension 160 a extends in the second direction Y. That is, the length in which the first extension 150 a extends in the direction from the distal end of the boundary region (INTERFACE) adjacent to the core region (CORE) toward the cell region (CELL) may be longer than the length in which the second extension 160 a extends in the direction from the distal end of the boundary region (INTERFACE) adjacent to the core region (CORE) toward the cell region (CELL).

Further, a third length L3 a in which the third extension 140 a extends in the second direction Y may be substantially the same as the second length L2 a. Accordingly, the region of the second extension 160 a corresponding to the first length L1 a may be disposed on the first extension 150 a. Further, the region of the second extension 160 a corresponding to a difference between the first length L1 a and the second length L2 a may be disposed on the third extension 140 a.

The recess 110 r formed on the upper surface of the boundary element isolation layer 110 a does not overlap the first and second extensions 150 a and 160 a and may be adjacent to at least one of the first and second extensions 150 a and 160 a.

As illustrated, when the first length L1 a is shorter than the second length L2 a, the recess 110 r may be adjacent to the second extension 160 a. Also, as illustrated, if the third length L3 a is substantially the same as the second length L2 a, the recess 110 r may be adjacent to the second and third extensions 160 a, and 140 a. At this time, the recess 110 r may not overlap the first and second extensions 150 a and 160 a.

Hereinafter, the boundary region of the semiconductor device according to some example embodiments of the present inventive concepts will be described with reference to FIG. 4b . For the sake of convenience of description, the repeated parts of the description of FIGS. 1 to 4 a will be briefly explained or omitted.

FIG. 4b is a diagram for illustrating a boundary region of a semiconductor device according to some example embodiments of the present inventive concepts.

FIG. 4b is a region corresponding to FIG. 4a . That is, the semiconductor device including the boundary region (INTERFACE) illustrated in FIG. 4b may be the same as the semiconductor device according to FIG. 3, except for a region D.

In some example embodiments, a first length L1 b in which the first extension 150 b extends in the second direction Y may be longer than a second length L2 b in which the second extension 160 b extends in the second direction Y. That is, the length in which the first extension 150 b extends in the direction from the distal end of the boundary region (INTERFACE) adjacent to the core region (CORE) toward the cell region (CELL) may be longer than the length in which the second extension 160 b extends in the direction from the distal end of the boundary region (INTERFACE) adjacent to the core region (CORE) toward the cell region (CELL). Accordingly, the region of the second extension 160 b corresponding to the second length L2 b may be disposed on the first extension 150 b.

Further, the third length L3 b in which the third extension 140 b extends in the second direction Y may be substantially the same as the first length L1 b.

As illustrated, when the first length Llb is longer than the second length L2 b, the recess 110 r may be adjacent to the first extension 160 b. Also, as illustrated, if the third length L3 b is substantially the same as the first length L1 b, the recess 110 r may be adjacent to the first and third extensions 150 b and 140 b. At this time, the recess 110 r may not overlap the first and second extensions 150 b and 160 b.

Hereinafter, a boundary region of a semiconductor device according to some example embodiments of the present inventive concepts will be described with reference to FIG. 4c . For the sake of convenience of description, the repeated parts of the description of FIGS. 1 to 4 a will be briefly explained or omitted.

FIG. 4c is a diagram for illustrating a boundary region of a semiconductor device according to some example embodiments of the present inventive concepts.

FIG. 4c is a region corresponding to FIG. 4a . That is, the semiconductor device including the boundary region (INTERFACE) according to FIG. 4c may be the same as the semiconductor device according to FIG. 3 except for a region D.

In some example embodiments, a first length L1 c in which the first extension 150 c extends in the second direction Y may be substantially the same as a second length L2 c in which the second extension 160 c extends in the second direction Y. That is, the length in which the first extension 150 c extends in the direction from the distal end of the boundary region (INTERFACE) adjacent to the core region (CORE) toward the cell region (CELL) may be substantially the same as the length in which the second extension 160 c extends in the direction from the distal end of the boundary region (INTERFACE) adjacent to the core region (CORE) toward the cell region (CELL). Accordingly, the region of the second extension 160 c corresponding to the first and second lengths L1 c and L2 c may be disposed on the first extension 150 c.

Further, a third length L3 c in which the third extension 140 c extends in the second direction Y may be substantially the same as the first and second lengths L1 c and L2 c.

As illustrated, when the first length L1 c is substantially the same as the second length L2 c, the recess 110 r may be adjacent to the first and second extensions 150 c and 160 c. Also, as illustrated, if the third length L3 b is substantially the same as the first and second lengths L1 b, the recess 110 r may be adjacent to the first to third extensions 150 b, 160 b and 140 b. At this time, the recess 110 r may not overlap the first and second extensions 150 c and 160 c.

Thus, in the semiconductor device according to some example embodiments of the present inventive concepts, it is possible to provide a semiconductor device with an improved degree of integration and reliability, while forming a high-k dielectric layer only in the core region.

The high-k dielectric layer 140 is not disposed on the substrate 100 of the cell region (CELL), and may be disposed on the substrate 100 of the core region (CORE). That is, the high-k dielectric layer 140 may be disposed only in the core region (CORE), without changing the structure of the bit line BL of the cell region (CELL). Therefore, a high-performance transistor driven with low power may be provided in the core region (CORE).

In addition, the gate insulating layer 130, the high-k dielectric layer 140, and the first and second work function metal patterns 150′ and 160′ disposed in the core region (CORE) may extend to a part of the interface region (INTERFACE). That is, the gate insulating layer 130, the high-k dielectric layer 140, the first and second work function metal patterns 150′ and 160′ may also be disposed on the substrate 100 of the core region (CORE) adjacent to the boundary region (INTERFACE). Accordingly, the substrate 100 of the core region (CORE) adjacent to the boundary region (INTERFACE) may also be used as a transistor. That is, the area of the core region (CORE) may be minimized, and the degree of integration of the semiconductor memory element may be improved.

Further, the recess 110 r formed on the boundary element isolation layer 110 a may prevent a short circuit between the cell region (CELL) and the core region (CORE). That is, by forming the recess 110 r on the boundary element isolation layer 110 a, it is possible to prevent the first or second work function metal pattern 150′, 160′ from extending to the cell region (CELL). Therefore, the reliability of the semiconductor memory element may be improved.

Hereinafter, a method of fabricating a semiconductor device according to some example embodiments of the present inventive concepts will be described with reference to FIGS. 5 to 16. For the sake of convenience of explanation, the repeated parts of the description of FIGS. 1 to 4 c will be briefly explained or omitted.

FIGS. 5 to 16 are intermediate step diagram for explaining a method for fabricating a semiconductor device according to some example embodiments of the present inventive concepts.

Referring to FIG. 5, an element isolation layer 110 and a word line pattern 120 are provided on the substrate 100.

Specifically, the element isolation layer 110 may be formed on the substrate 100 of the cell region (CELL), the core region (CORE) and the boundary region (INTERFACE). At this time, the boundary element isolation layer 110 a may be formed on the substrate 100 of the boundary region (INTERFACE).

Subsequently, a word line trench may be formed on the substrate 100 of the cell region (CELL). A buried dielectric layer 126, a buried conductive layer 124, and a buried insulating layer 122 may be sequentially buried in the formed word line trench to form the word line pattern 120. At this time, although the word line pattern 120 may be formed on the element isolation layer 110, the example embodiments of the present disclosure are not limited thereto, and the word line pattern 120 may not be formed on the element isolation layer 110.

Referring to FIG. 6, first and second insulating layers 202 and 204 are formed on the substrate 100 of the cell region (CELL).

Specifically, the first and second insulating layers 202 and 204 are sequentially formed on the substrate 100, the element isolation layer 110 and the word line pattern 120 of the cell region (CELL).

Although the first insulating layer 202 may be formed of an oxide layer and the second insulating layer 204 may be formed of a nitride layer, the example embodiments of the present disclosure are not limited thereto.

Referring to FIG. 7, a gate insulating layer 130 is formed on the substrate 100 of the core region (CORE).

For example, the gate insulating layer 130 may be formed by oxidization of the substrate 100. Accordingly, the gate insulating layer 130 may include an oxide of the substrate 100. Further, the gate insulating layer 130 may be formed on the substrate 100 of the core region (CORE), and may not be formed on the element isolation layer 110.

However, the example embodiments of the present disclosure are not limited thereto, and the gate insulating layer 130 may be formed on the substrate 100 and the element isolation layer 110 of the core region (CORE) by another process such as ALD (atomic layer deposition). Further, the gate insulating layer 130 may be formed on the boundary element isolation layer 110 a.

Referring to FIG. 8, the high-k dielectric layer 140 is formed on the result of FIG. 7.

For example, the high-k dielectric layer 140 may be formed on the substrate 100 by a process such as a chemical vapor deposition (CVD) or an atomic layer deposition (ALD).

Accordingly, the high-k dielectric layer 140 may be conformally formed on the result of FIG. 7. That is, the high-k dielectric layer 140 may be formed on the first and second insulating layers 202 and 204 in the cell region (CELL), may be formed on the boundary element isolation layer 110 a in the boundary region (INTERFACE), and may be formed on the gate insulating layer 130 in the core region (CORE).

Referring to FIG. 9, a first work function metal layer 150 is formed on the high-k dielectric layer 140. The first work function metal layer 150 may be conformally formed on the high-k dielectric layer 140.

For example, the first work function metal layer 150 may be formed of tungsten (W), tantalum (Ta), aluminum (Al), ruthenium (Ru), platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), or a combination thereof.

Further, the first work function metal layer 150 may be formed with a multi-layer structure by laminating a plurality of thin metal layers. For example, the first work function metal layer 150 may be formed of Al₂O₃/TiN, Al₂O₃/TaN, Al/TiN, Al/TaN, TiN/Al/TiN, TaN/Al/TaN, TiN/TiON, TaN/TiON, Ta/TiN, TaN/TiN, or a combination thereof.

Referring to FIG. 10, a first photoresist 300 is formed on the first work function metal layer 150.

Specifically, the first photoresist 300 may be formed to overlap at least a part of the boundary element isolation layer 110 a and the first region I. Further, the first photoresist 300 may be formed so as not to overlap the second region II.

At this time, the first photoresist 300 may be formed to overlap the boundary element isolation layer 110 a by a first length L1. That is, the first photoresist 300 may extend by a first length L1 in the direction from the distal end of the boundary region (INTERFACE) adjacent to the core region (CORE) toward the cell region (CELL).

Referring to FIG. 11, the first work function metal layer 150 is patterned using the first photoresist 300 as an etch mask. As a result, the first work function metal layer 150 may be patterned to form the first work function metal pattern 150′.

Specifically, the first work function metal pattern 150′ may be performed by a photolithography process. That is, the first work function metal layer 150 which does not overlap the first photo resist 300 is removed, the remaining first work function metal layer 150 may form the first work function metal pattern 150′.

As a result, the first work function metal pattern 150′ may extend by the first length L1 in the direction from the distal end of the boundary region (INTERFACE) adjacent to the core region (CORE) toward the cell region (CELL).

After forming the first work function metal pattern 150′, the first photoresist 300 may be removed.

In some example embodiments, the high-k dielectric layer 140 may be used as an etch stop layer. As a result, when the first work function metal layer 150 is patterned, the high-k dielectric layer 140 may not be patterned.

Referring to FIG. 12, a second work function metal layer 160 is formed on the result of FIG. 11. The second work function metal layer 160 may be conformally formed on the resultant of FIG. 11.

For example, the second work function metal layer 160 may be formed of lanthanum (La), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), titanium nitride (TiN), or a combination thereof.

Further, the second work function metal layer 160 may be formed of a multi-layer structure by laminating a plurality of thin metal layers. For example, the second work function metal layer 160 may be formed of TiN/TiON, Mg/TiN, TiN/Mg/TiN, La/TiN, TiN/La/TiN, Sr/TiN, TiN/Sr/TiN, or a combination thereof.

Referring to FIG. 13, a second photoresist 310 is formed on the second work function metal layer 160.

Specifically, the second photoresist 310 may be formed to overlap at least a part of the boundary element isolation layer 110 a and the first and second regions I and II.

At this time, the second photoresist 310 may be formed to overlap the boundary element isolation layer 110 a by the second length L2. That is, the second photoresist 310 may extend by the second length L2 in the direction from the distal end of the boundary region (INTERFACE) adjacent to the core region (CORE) toward the cell region (CELL).

In some example embodiments, the second length L2 may be formed to be different from the first length L1. That is, formation of the second photoresist 310 may include formation of the length of the second photoresist 310 overlapping the boundary element isolation layer 110 a different from the length of the first photoresist 300 overlapping the boundary element isolation layer 110 a.

For example, when the second length L2 is formed to be longer than the first length L1, the second photoresist 310 may completely cover the first work function metal pattern 150′.

Referring to FIG. 14, the second work function metal layer 160 is patterned using the second photoresist 310 as an etching mask. Thus, the second work function metal layer 160 may be patterned to form the second work function metal pattern 160′.

Specifically, formation of the second work function metal pattern 160′ may be performed by a photolithography process. That is, the second work function metal layer 160 which does not overlap the second photoresist 310 is removed, and the remaining second work function metal layer 160 may form the second work function metal pattern 160′.

As a result, the second work function metal pattern 160′ may extend by a second length L2 in the direction from the distal end of the boundary region (INTERFACE) adjacent to the core region (CORE) toward the cell region (CELL).

After forming the second work function metal pattern 160′, the second photoresist 310 may be removed.

In some example embodiments, the second work function metal layer 160 and the high-k dielectric layer 140 may be simultaneously patterned, using the second photoresist 310 as an etching mask. That is, patterning of the second work function metal layer 160 may include patterning of the high-k dielectric layer 140, using the second photoresist 310 as an etching mask.

For example, when the second length L2 is formed to be longer than the first length L1, the second work function metal pattern 160′ and the high-k dielectric layer 140 may extend by the second length L2 in the direction from the distal end of the boundary region (INTERFACE) adjacent to the cell region (CORE) toward the cell region (CELL).

At this time, a part of the upper portion of the boundary element isolation layer 110 a may be etched to form the recess 110 r. Specifically, the second work function metal layer 160 and the high-k dielectric layer 140 exposed by the second photoresist 310 may be patterned to expose a part of the upper portion of the boundary element isolation layer 110 a. As a result, a part of the upper portion of the exposed boundary element isolation layer 110 a may be etched to form the recess 110 r.

For example, when the second length L2 is formed to be longer than the first length L1, the recess 110 r may be formed to be adjacent to the second work function metal layer 160 and the high-k dielectric layer 140.

Referring to FIG. 15, a direct contact pattern 210 is formed on the substrate 100 of the cell region (CELL). Subsequently, the first to third conductive layers 222, 224 and 226 and the capping layer 230 are sequentially laminated on the substrate 100.

Specifically, a direct contact trench may be formed through the first and second insulating layers 202 and 204 to expose a part of the substrate 100 of the cell region (CELL). Subsequently, the direct contact trench is buried and the direct contact pattern 210 may be formed.

Subsequently, the first to third conductive layers 222, 224 and 226 and the capping layer 230 may be conformally formed on the substrate 100. The first conductive layer 222 may include, for example, the same material as the direct contact pattern 210, but the example embodiments of the present disclosure are not limited thereto.

Referring to FIG. 16, the result of FIG. 15 is patterned. Subsequently, a gate spacer 240 is formed on the side wall of the structure formed in the first and second regions I and II. Therefore, the semiconductor device according to FIG. 3 may be formed.

For example, in FIG. 13, when the second length L2 is formed to be longer than the first length L1, the boundary region (INTERFACE) of the semiconductor device according to some example embodiments of the present inventive concepts may be the same as that of FIG. 4 a.

For example, in FIG. 13, when the second length L2 is formed to be shorter than the first length L1, the boundary region (INTERFACE) of the semiconductor device according to some example embodiments of the present inventive concepts may be the same as that of FIG. 4 b.

For example, in FIG. 13, when the second length L2 is formed to be substantially the same as the first length L1, the boundary region (INTERFACE) of the semiconductor device according to some example embodiments of the present inventive concepts may be the same as that of FIG. 4 c.

Accordingly, the method for fabricating the semiconductor device according to some example embodiments of the present inventive concepts may provide a method for fabricating a semiconductor device in which the degree of integration and reliability are improved, while forming a high-k dielectric layer only in the core region.

While the present inventive concepts have been particularly illustrated and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present inventive concepts as defined by the following claims. The example embodiments should be considered in a descriptive sense only and not for purposes of limitation. 

1. A semiconductor device comprising: a substrate including a cell region, a core region, and a boundary region between the cell region and the core region; an element isolation layer in the boundary region of the substrate; a dielectric layer in the boundary region and the core region of the substrate; a first conductive pattern on the dielectric layer and including a first extension portion in the boundary region of the substrate; a second conductive pattern on the first conductive pattern and including a second extension portion in the boundary region of the substrate; and a third conductive pattern on the second conductive pattern and including a third extension portion in the boundary region of the substrate, wherein a length of the second extension portion of the second conductive pattern is greater than a length of the first extension portion of the first conductive pattern, and is less than a length of the third extension portion of the third conductive pattern, and the third extension portion of the third conductive pattern contacts the element isolation layer.
 2. The semiconductor device of claim 1, wherein the dielectric layer includes a fourth extension portion in the boundary region, and a length of the fourth extension portion of the dielectric layer is greater than the length of the first extension portion of the first conductive pattern.
 3. The semiconductor device of claim 2, wherein the length of the second extension portion of the second conductive pattern is substantially same as the length of the fourth extension portion of the dielectric layer.
 4. The semiconductor device of claim 1, wherein the second extension portion of the second conductive pattern contacts a side surface of the first extension portion of the first conductive pattern.
 5. The semiconductor device of claim 1, wherein the third extension portion of the third conductive pattern contacts a side surface of the second extension portion of the second conductive pattern.
 6. The semiconductor device of claim 2, wherein the third extension portion of the third conductive pattern contacts a side surface of the fourth extension portion of the dielectric layer.
 7. The semiconductor device of claim 1, wherein the third extension portion of the third conductive pattern is spaced apart from the first extension portion of the first conductive pattern.
 8. The semiconductor device of claim 1, wherein the element isolation layer includes a recess adjacent to the third extension portion of the third conductive pattern, and the recess is spaced apart from the first extension portion of the first conductive pattern.
 9. The semiconductor device of claim 1, wherein the dielectric layer includes at least one of a gate insulating layer or a high-k dielectric layer having a dielectric constant higher than a dielectric constant of the gate insulating layer, the first conductive pattern includes at least one of tungsten (W), tantalum (Ta), aluminum (Al), ruthenium (Ru), platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), or tantalum carbide (TaC), the second conductive pattern includes at least one of lanthanum (La), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), or titanium nitride (TiN), and the third conductive pattern includes at least one of polysilicon, TiN, TiSiN, tungsten, or tungsten silicide.
 10. The semiconductor device of claim 1, wherein the core region of the substrate includes a first core region and a second core region, the first core region includes the dielectric layer, the first conductive pattern on the dielectric layer, and the second conductive pattern on the first conductive pattern, and the second core region includes the dielectric layer and the second conductive pattern on the dielectric layer.
 11. The semiconductor device of claim 1, wherein a top surface of the third extension portion of the third conductive pattern is lower than a top surface of the third conductive pattern in the core region.
 12. The semiconductor device of claim 1, further comprising: a bit line that is disposed in the cell region, wherein a top surface of the element isolation layer is exposed between the third extension portion of the third conductive pattern and the bit line, and the top surface of the element isolation layer includes a recess.
 13. The semiconductor device of claim 12, wherein each of the bit line and the third conductive pattern includes polysilicon, TiSiN and tungsten.
 14. A semiconductor device comprising: a substrate including a cell region, a core region, and a boundary region between the cell region and the core region; a boundary element isolation layer in the boundary region of the substrate; a high-k dielectric layer in the boundary region and the core region of the substrate; a first conductive pattern on the high-k dielectric layer and including a first extension portion in the boundary region of the substrate; a second conductive pattern on the first conductive pattern and including a second extension portion in the boundary region of the substrate; a third conductive pattern on the second conductive pattern and including a third extension portion in the boundary region of the substrate; and a bit line disposed in the cell region, wherein a top surface of the boundary element isolation layer is exposed between the third extension portion of the third conductive pattern and the bit line, the top surface of the boundary element isolation layer includes a recess, a length of the second extension portion of the second conductive pattern is greater than a length of the first extension portion of the first conductive pattern, and is less than a length of the third extension portion of the third conductive pattern, the high-k dielectric layer includes a fourth extension portion in the boundary region, and a length of the fourth extension portion of the high-k dielectric layer is greater than the length of the first extension portion of the first conductive pattern.
 15. The semiconductor device of claim 14, wherein the third extension portion of the third conductive pattern contacts the boundary element isolation layer.
 16. The semiconductor device of claim 14, wherein the length of the second extension portion of the second conductive pattern is substantially as the length of the fourth extension portion of the high-k dielectric layer.
 17. The semiconductor device of claim 14, wherein the second extension portion of the second conductive pattern contacts a side surface of the first extension portion of the first conductive pattern.
 18. The semiconductor device of claim 14, wherein the third extension portion of the third conductive pattern contacts at least one of a side surface of the second extension portion of the second conductive pattern or a side surface of the fourth extension portion of the high-k dielectric layer.
 19. A semiconductor device comprising: a substrate including a cell region, a core region, and a boundary region between the cell region and the core region; a boundary element isolation layer in the boundary region of the substrate; a high-k dielectric layer in the boundary region and the core region of the substrate; a first conductive pattern on the high-k dielectric layer and including a first extension portion in the boundary region of the substrate; a second conductive pattern on the first conductive pattern and including a second extension portion in the boundary region of the substrate; and a third conductive pattern on the second conductive pattern and including a third extension portion in the boundary region of the substrate, wherein the high-k dielectric layer includes a fourth extension portion in the boundary region, a length of the second extension portion of the second conductive pattern is greater than a length of the first extension portion of the first conductive pattern, and is less than a length of the third extension portion of the third conductive pattern, and the length of the second extension portion of the second conductive pattern is substantially same as the length of the fourth extension portion of the high-k dielectric layer.
 20. The semiconductor device of claim 19, wherein the third extension portion of the third conductive pattern contacts the boundary element isolation layer. 